1. Technical Field
The disclosure in generally relates to a semiconductor device and a method for fabricating the same, and more particularly to a memory device and a method for fabricating the same.
2. Description of the Related Art
Non-volatile memory (NVM) which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell has been adopted by bulk solid state memory applications in portable audiovisual entertainment devices, cell phones or digital cameras etc. Recently, various three dimensional (3D) memory devices, such as a 3D flash memory device having a single gate, a double gate or a surrounding gate, has been provided in order to accommodate the rising demand for superior memory.
A 3D memory device, such as a vertical-channel (VC) 3D NAND flash memory device that has a multi-layer stack structure may possess a higher density memory and excellent electrical characteristics, e.g. reliability in data storage and high operating speed. As semiconductor features shrink in size and pitch, the parasitic resistance-capacitance (RC) time delays caused by the resistance and capacitance of interconnect conductive lines, such as the word lines or the source lines, may reversely affect the operating speed and reliability of the VC 3D flash memory device. In order to solve these problems, a VC 3D flash memory device with metal gate has been provided.
However, there are still some problems in applying a VC 3D NAND flash memory device with a metal gate. During the process foe fabricating the VC 3D flash memory device, etch trenches passing through a multi-layer stack structure of the VC 3D NAND flash memory device for performing an etching process to remove sacrifice layers and allowing metal gates (word lines) formed on the position where the sacrifice layers originally disposed may be required. However, the etch trenches may occupy space of the multi-layer stack structure and exclude the forming of memory cells. The memory storage density of the VC 3D NAND flash memory device may thus be reduced. Furthermore, the residue of the sacrifice layers may remained in the multi-layer stack structure after the etching process for removing the sacrifice layers is carried out, or otherwise the memory layers could be damaged by over etch while the residue is thoroughly removed by a more aggressive etching process. As a result, defect memory cells may occur and the yield of the VC 3D NAND flash memory device may be also reduced.
Therefore, there is a need of providing an improved memory device and a method for fabricating the same to obviate the drawbacks encountered from the prior art.